TAN, H. H.; AHMAD, N.; NGADENGON, R.; SIA, P. Y. Y.; MUTHU, A. E. R. FPGA-Based Design for Digital Speedometer to Detect Speed Limit of Vehicles. Journal of Advanced Research in Applied Mechanics, [S. l.], v. 127, n. 1, p. 183–200, 2024. DOI: 10.37934/aram.127.1.183200. Disponível em: https://semarakilmu.com.my/journals/index.php/appl_mech/article/view/4832. Acesso em: 21 dec. 2024.