1.
Tan HH, Ahmad N, Ngadengon R, Sia PYY, Muthu AER. FPGA-Based Design for Digital Speedometer to Detect Speed Limit of Vehicles. J. Adv. Res. Appl. Mech. [Internet]. 2024 Nov. 30 [cited 2024 Dec. 21];127(1):183-200. Available from: https://semarakilmu.com.my/journals/index.php/appl_mech/article/view/4832