[1]
Kaharudin, K.E., Jalaludin, N.A., Salehuddin, F., Arith, F., Mohd Zain, A.S., Ahmad, I., Mat Junos, S.A. and Apte, P.R. 2024. A Predictive Approach to Reduce Intrinsic Gate Delay in Junctionless Double Gate Strained Transistor using DoE-Based Genetic Algorithm. Journal of Advanced Research in Applied Sciences and Engineering Technology. (Oct. 2024), 38–51. DOI:https://doi.org/10.37934/araset.59.1.3851.