(1)
Kaharudin, K. E.; Jalaludin, N. A.; Salehuddin, F.; Arith, F.; Mohd Zain, A. S.; Ahmad, I.; Mat Junos, S. A.; Apte, P. R. A Predictive Approach to Reduce Intrinsic Gate Delay in Junctionless Double Gate Strained Transistor Using DoE-Based Genetic Algorithm. J. Adv. Res. Appl. Sci. Eng. Tech. 2024, 38-51.