KAHARUDIN, K. E.; JALALUDIN, N. A.; SALEHUDDIN, F.; ARITH, F.; MOHD ZAIN, A. S.; AHMAD, I.; MAT JUNOS, S. A.; APTE, P. R. A Predictive Approach to Reduce Intrinsic Gate Delay in Junctionless Double Gate Strained Transistor using DoE-Based Genetic Algorithm. Journal of Advanced Research in Applied Sciences and Engineering Technology, [S. l.], p. 38–51, 2024. DOI: 10.37934/araset.59.1.3851. Disponível em: https://semarakilmu.com.my/journals/index.php/applied_sciences_eng_tech/article/view/6004. Acesso em: 19 nov. 2024.