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Kaharudin KE, Jalaludin NA, Salehuddin F, Arith F, Mohd Zain AS, Ahmad I, Mat Junos SA, Apte PR. A Predictive Approach to Reduce Intrinsic Gate Delay in Junctionless Double Gate Strained Transistor using DoE-Based Genetic Algorithm. J. Adv. Res. Appl. Sci. Eng. Tech. [Internet]. 2024 Oct. 8 [cited 2024 Nov. 19];:38-51. Available from: https://semarakilmu.com.my/journals/index.php/applied_sciences_eng_tech/article/view/6004