JIA YANG HOR; CHIA YEE OOI; SOON CHIEH LIM. Register Transfer Level Design of 32-Bit RISC-V Out-of-Order Processor. Semarak Engineering Journal, [S. l.], v. 2, n. 1, p. 1–7, 2023. Disponível em: https://semarakilmu.com.my/journals/index.php/sem_eng/article/view/6225. Acesso em: 22 dec. 2024.