Register Transfer Level Design of 32-Bit RISC-V Out-of-Order Processor

Abstract

This work demonstrates the performance boost brought by a RISC-V out-of-order processor. In this work, we design a 32-bit RISC-V out-of-order processor using RTL methodology, unlocking the potential of out-of-order execution for enhanced performance in RISC-V processors. By comparing the out-of-order and in-order processors, this work highlights the limitations of the latter. The work focuses on Verilog code and the Synopsys VCS compiler [15] for designing both processors, with observation facilitated by the DVE waveform viewer. The RTL design process includes load buffers, reservation stations for adders and multipliers, and effective hazard and dependency handling through stall mechanisms. Incorporating the Tomasulo algorithm enables dynamic instruction scheduling in the out-of-order processor. This work’s outcome is an RTL design of a 32-bit RISC-V out-of-order processor, demonstrating improved performance compared to the in-order processor [1]. This work sheds light on the advantages of out-of-order execution and paves the way for further research in advanced RISC-V processors. The results will showcase the significant advantage of the RISC-V out-of-order processor over the in-order processor, offering a glimpse into the exciting possibilities that out-of-order execution brings to the RISC-V architecture, leaving readers eager to delve deeper into the potential impact of this innovation.