Integrating Design for Testability Technique into OpenLane with Skywater 130-Nanometer Process Design Kit

Abstract

This paper highlights the key findings and outcomes of a case study on the implementation of the SHA-1 design using OpenLANE and the SkyWater 130-nanometer process design kit. The study demonstrates the successful execution of various analyses and checks, including static timing analysis, design rule check (DRC), and layout vs schematic (LVS) verification. The results indicate that the design meets timing requirements, complies with manufacturing regulations, and accurately reflects the intended schematic circuit. The implementation of a scan chain in the design using Fault is also discussed. The study further explores the area, power consumption, timing analysis of the SHA-1 chip, providing insights for optimization and future developments. The result on this project has passed design rule check and layout vs schematic with period of 11.87ns and 14.62ns for case 1 and case 2 respectively. Overall, this case study emphasizes the efficacy and reliability of OpenLANE in RTL-to-GDS implementation and underlines the commitment to open-source development.