Hardware Implementation of Hough Transform for the Application in Lane Detection in Smart Vehicles

Abstract

Lane detection is one of the important features of smart vehicles. It is used to assist drivers in achieving the best driving experience. Lane detection utilizes the line detection algorithm where there are many algorithms that are available, but the most effective algorithm is the Hough Transform because it is simple and can be applied in both software and hardware implementations. However, studies shown that Hough Transform implementation of video in the software environment could result in sub-par performance because it requires extremely high computation resources and memory. Therefore, we propose hardware implementation of the Hough Transform for lane detection in this work. The targeted hardware is the Field Programmable Logic Array (FPGA) as its reconfigurable nature allows for rapid design. Hardware implementation of video processing enables parallel data processing, which reduces overall system latency. Furthermore, the hardware design can be optimized to reduce the number of logics that will lead to lower power consumption. The hardware logics were designed based on the Hough Transform equation by using the Verilog Hardware Description Language (HDL) in Intel Quartus Prime software. After the design is successfully completed and verified through simulation, the execution speed of the hardware implementation is then compared with the same design in the software environment (MATLAB). The results show that Hough Transform implemented on the hardware is more than 100 times faster than the software implementation. The total number of logic elements is less than 1% of logic resources, resulting in low power consumption at 146 mW.