Design of High-Performance Mini Crypto-Core using PRESENT Block Cipher on FPGA

Abstract

The PRESENT algorithm is a lightweight cryptographic algorithm crucial in securing data in the emerging pervasive computing environment. This research focuses on developing a high-performance PRESENT-based crypto-core, leveraging the advantages of this algorithm. The hardware design is implemented in VHDL using the FPGA approach on an Intel MAX 10 device (10M08DAF484C8G). Functional simulation and performance analysis are conducted using ModelSim-Intel FPGA and Altera Quartus Prime Lite. The simulation and analysis results demonstrate that the encryption process of the crypto-core utilizes 292 logic elements and 152 registers. In comparison, the decryption process uses 402 logic elements and 244 registers. The design achieves encryption and decryption speeds of 10.436 ns and 10.992 ns, respectively. The total power consumption of the crypto-core is measured at 46.23 mW. Additionally, the designed crypto-core exhibits satisfactory throughput, achieving 133.33 Mbps for encryption and 63.68 Mbps for decryption. In conclusion, the developed PRESENT-based crypto-core demonstrates optimal performance on FPGA.