Predictive Placement of IC Chips using ANN-GA Approach for Efficient Thermal Cooling

Authors

  • Anant Sidhappa Kurhade Department of Mechanical Engineering, Dr. D. Y. Patil Institute of Technology Pimpri, Pune, Maharashtra 411018, India
  • Ramdas Biradar School of Engineering & Technology, PCET’s Pimpri Chinchwad University, Sate, 412106, Pune, Maharashtra, India
  • Rahul Shivaji Yadav Department of Mechanical Engineering, Marathwada Mitra Mandal's College of Engineering, Karvenagar, Pune, 411052, Maharashtra, India
  • Prashant Patil Department of Mechanical Engineering, Abhinav Education Society's College of Engineering & Technology, Pune, 411046, Maharashtra, India
  • Nitin Babanrao Kardekar Department of Mechanical Engineering, Bhivarabai Sawant College of Engineering and Research, Pune, 411041, Maharashtra, India
  • Shital Yashwant Waware Department of Mechanical Engineering, Dr. D. Y. Patil Institute of Technology Pimpri, Pune, Maharashtra 411018, India
  • Kashinath Haribhau Munde Department of Mechanical Engineering, KES Rajarambapu Institute of Technology, Lohagaon, Pune, 411047, Maharashtra, India
  • Ajitkumar Gulab Nimbalkar Department of Mechanical Engineering, Marathwada Mitra Mandal's College of Engineering, Karvenagar, Pune, 411052, Maharashtra, India
  • Govindarajan Murali Department of Mechanical Engineering Koneru Lakshmaiah Education Foundation Green Fields, Vaddeswaram, Guntur (Dt) Andhra Pradesh 522502, India

DOI:

https://doi.org/10.37934/arfmts.118.2.137147

Keywords:

ANN, ANSYS Icepack, GA, IC chips, optimal configuration

Abstract

In this research, numerical modelling is used to explore the heat transfer through natural convection capabilities of nine aluminum integrated circuit chips that are installed on substrate board. The goal is to figure out where on the substrate board these IC chips would be best placed if they were arranged differently. The dimensionless parameter (λ) plays a very essential role, and by applying a hybrid technique consisting of ANN and GA. ANSYS Icepack calculates IC chip temperature distributions in 3D steady state numerical simulations. It has been shown that the form, dimensions, and IC chips' substrate board positioning affects their operating temperature. In comparison to the strategies that have been used in the past, hybrid optimization is the strategy that has shown to be the most reliable in properly predicting how the IC chips would be arranged on the substrate board. It has been observed that higher values of one of these parameters lead to a reduction in the maximum temperature surplus. A correlation has been established to illustrate this relationship as it increases. The most favorable simulation outcomes are utilized to drive a genetic algorithm (GA), which identifies the optimal configuration ensuring that the temperatures of the heat sources remain well below their specified maximum operating conditions, as outlined in the data sheets. The maximum temperature variation between the lowest and highest extreme configurations ranges between 4 - 8%. The smallest size IC chip, U2 with high heat dissipation rate attains the maximum temperature in the configuration, however, the temperature variation for the low powered IC chips U3, U4 and U7 are very small. Found good agreement of both the data with an error band of 10%, and thus confirms the accuracy of the network.

Author Biographies

Anant Sidhappa Kurhade, Department of Mechanical Engineering, Dr. D. Y. Patil Institute of Technology Pimpri, Pune, Maharashtra 411018, India

a.kurhade@gmail.com

Ramdas Biradar, School of Engineering & Technology, PCET’s Pimpri Chinchwad University, Sate, 412106, Pune, Maharashtra, India

ramdas.biradar@pcu.edu.in

Rahul Shivaji Yadav, Department of Mechanical Engineering, Marathwada Mitra Mandal's College of Engineering, Karvenagar, Pune, 411052, Maharashtra, India

yahulyadav491@gmail.com

Prashant Patil, Department of Mechanical Engineering, Abhinav Education Society's College of Engineering & Technology, Pune, 411046, Maharashtra, India

pjpatil76@rediffmail.com

Nitin Babanrao Kardekar, Department of Mechanical Engineering, Bhivarabai Sawant College of Engineering and Research, Pune, 411041, Maharashtra, India

nitinkardekar.n@gmail.com

Shital Yashwant Waware, Department of Mechanical Engineering, Dr. D. Y. Patil Institute of Technology Pimpri, Pune, Maharashtra 411018, India

shital.221p0009@viit.ac.in

Kashinath Haribhau Munde, Department of Mechanical Engineering, KES Rajarambapu Institute of Technology, Lohagaon, Pune, 411047, Maharashtra, India

kashinathmunde@gmail.com

Ajitkumar Gulab Nimbalkar, Department of Mechanical Engineering, Marathwada Mitra Mandal's College of Engineering, Karvenagar, Pune, 411052, Maharashtra, India

nimbalkarag777@gmail.com

Govindarajan Murali, Department of Mechanical Engineering Koneru Lakshmaiah Education Foundation Green Fields, Vaddeswaram, Guntur (Dt) Andhra Pradesh 522502, India

drmurali@kluniversity.in

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Published

2024-06-30

How to Cite

Anant Sidhappa Kurhade, Ramdas Biradar, Rahul Shivaji Yadav, Prashant Patil, Nitin Babanrao Kardekar, Shital Yashwant Waware, Kashinath Haribhau Munde, Ajitkumar Gulab Nimbalkar, & Govindarajan Murali. (2024). Predictive Placement of IC Chips using ANN-GA Approach for Efficient Thermal Cooling. Journal of Advanced Research in Fluid Mechanics and Thermal Sciences, 118(2), 137–147. https://doi.org/10.37934/arfmts.118.2.137147

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