FPGA-Based Design for Digital Speedometer to Detect Speed Limit of Vehicles

Abstract

This paper presents a proposed design for a digital speedometer using Field Programmable Gate Array (FPGA) technology. The speedometer is a crucial safety feature in vehicles, providing real-time information on the vehicle's speed in kilometres per hour (km/h). The objective of this design is to assist drivers in monitoring and controlling their velocity at regular intervals to ensure safe driving. The hardware platform chosen for implementation is the Altera DE2 Board with Cyclone IV E and the hardware description language used is Verilog HDL. The digital speedometer receives a square wave pulse as an input signal from a hall sensor, which is emitted based on the vehicle's speed. The designed system accurately detects and counts these pulses to convert them into the corresponding speed of the vehicle. This digital speedometer is specifically intended for vehicles with engine capacities (cc) ranging from 1000cc to 1300cc. It can detect speeds within the range of 0km/h to 255km/h. The speed value is displayed on a seven-segment display with precision. Additionally, if the vehicle's speed exceeds the expressway's speed limit of 110km/h, a red LED indicator turns on to alert the driver to control their speed.