Approximate Square and Square Root Calculation without Multiplication or Division for DSP Applications

Abstract

Square and square root functions are a fundamental step in many real-time digital signal processing applications such as image processing, signal processing, and filtering. The evaluation performance of these applications depends on the hardware algorithm used in the implementation of the square and square-root calculation. In this paper, we present an efficient algorithm that is capable of performing square and square root calculations without multiplication or division. Multiplier-less circuitry is introduced throughout the architecture to avoid the use of costly multipliers and dividers. The proposed square and square-root design exhibit good performance according to accuracy, latency, and power dissipation. Implementation and synthesis using Synopsys Design Compiler with a 90 nm CMOS process, 1.0 V supply voltage standard cell library, demonstrates that the proposed architecture leads to a 45% reduction in power dissipation while achieving higher accuracy when compared to the state-of-the-art approximate architectures. In addition, the proposed architecture is able to process the square and square-root calculation in 3 ns.